As the size of wafer level package devices increases, the array of solder connections between the wafer level package (WLP) device and a printed circuit board also increases. Referring to FIG. 1, a portion of a bottom or underside view of an under bump metal to solder ball interface is shown. In particular, FIG. 1 shows an under bump metal to solder joint interface within a solder joint array that is located adjacent to a wafer level package corner. For clarity, the solder ball is not depicted in FIG. 1. FIG. 2 is a cut away view along cut away line A of FIG. 1. Referring now to both FIGS. 1 and 2, a portion of a prior art wafer level package 100 is shown. FIG. 2 depicts various material layers associated with the WLP 100. A silicon layer 102 is shown. Within the silicon layer 102 is the active area 104 of the silicon layer wherein on chip semiconductor circuitry is found. The active area 104 ends near each edge of a WLP resulting in a narrow edge area or inactive area 106 that extends about the exterior edges or periphery of the WLP 100 as shown in FIG. 1. Underneath the silicon layer 102 and the active area 104 is a passivation layer 108. The passivation layer is an oxide material that essentially insulates the semiconductor circuitry (not specifically shown) within the active area 104 of the silicon layer 102. Next to the passivation layer 108 is a dielectric layer 110. Within the dielectric layer 110 is a redistribution layer (RDL) 112. The RDL 112 is a metal layer that is responsible for electrically connecting the semiconductor circuitry within the silicon 102 to an exterior connection, for example, to a solder ball 124 and in turn a PC board.
In some WLP devices, the dielectric layer 110 is put down in two separate layers or steps, shown via the dotted line between the two areas indicated as being the dielectric layer 110. The redistribution layer 112 depicted comprises RDL pads and signal trace lines (not specifically shown). Against an RDL pad 112 is an underbump layer (UBM) 116 having a cupped shape such that a solder ball 124 can be easily placed on the UBM 116. The UBM 116 depicted is sometimes referred to as a UBM pad 116. An inner diameter 122 of the UBM 116 is sometimes referred to as the dielectric opening diameter 122, which allows for electromigration of signals, currents and voltages to and from the active circuitry on the silicon 102 via the UBM pad 116 and the RDL pad 112. The RDL pad 112 is electrically connected to the active circuitry within the silicon 102. In some prior art devices, the UBM pad diameter 118 is the same or similar in size to the RDL pad diameter 114. In other prior art, the UBM pad diameter is about zero to 10 microns larger than the RDL pad diameter. As shown, there is some amount of dielectric that separates the RDL lip or edge 115 from the UBM lip or edge. Generally, in prior art devices, the RDL lip 115 has a radial width of from about 0 to about 13 microns.
As wafer level packages become larger their associated solder ball grid arrays or solder joint arrays have also increased in dimension. As the solder ball grid arrays become larger than 7×7 it was found that the prior art wafer level packages began to fail and become less reliable during temperature cycle (TC) testing and drop testing (DT). The TC and DT tests are common reliability tests performed on WLP devices to ensure that they meet minimum reliability standards. During both the TC and the DT testing, the larger WLPs exhibit a die level crack more frequently as the size of the WLP package increase length, width and solder ball count.
Referring to FIG. 3, a prior art WLP structure 100 is shown having both a primary 300 and secondary 306 crack depicted. The primary failure mode of the prior art WLP structure 100 during a temperature cycle and/or drop test is due to a dielectric and passivation layer crack. The primary crack 300 initializes at an upper edge portion of the RDL lip 115. The initialization of this crack during the temperature cycling is believed to be due to the differing coefficients of expansion and contraction of the various layers of materials near and about the solder ball 124, the solder joint and the printed circuit card connection.
There is a high tensile stress concentration created during the TC and drop tests. This stress concentration transfers from the strong UBM pad 116 to the RDL pad 112, which shifts the stress via the RDL lip 115 into the dielectric 110. It is common that the dielectric crack initiates at the RDL lip 115 and then propagates toward the passivation layer 108. In short, during temperature cycling, stress accumulates in the solder joints and shifts to the dielectric layer 110 through the RDL edge 115. As shown, the crack can extend through the dielectric layer and then through the passivation layer at 302 when the crack continues into the silicon 102 and active circuit area (see 304), a circuit failure results.
It is the tensile stress concentration that develops during the TC loading due to the coefficient of thermal expansion mismatch between the printed circuit board (not shown) and the WLP that causes the cracking and failure.
A secondary crack 306 often occurs, but the secondary crack does not create additional failure. The secondary crack 306 travels from the RDL lip 115 toward the UBM layer 116 and does not generally break any electrical connections.
Thus, a problem with prior art WLP devices is that the stress level on the RDL is too high during temperature cycling and drop testing causing a crack or failure through the dielectric layer 110 and into the integrated circuitry. What is needed is a method or mechanism that can decrease or spread the stress buildup on or around the RDL pads during temperature cycling and drop testing of WLPs having a grid array greater than a 7×7 solder joint connection array in order to increase the reliability and mean time between failure of such larger WLP die sizes being manufactured. There is a need for the reliability of large array wafer level packages (LAWLP) to withstand the stresses of temperature cycling and drop testing with high success rather than failure rates.